The present invention relates to a semiconductor memory device; and, the invention relates to a technology that is effective for application to a device in which word lines and bit lines connected to dynamic memory cells are respectively divided into plural forms and which has hierarchical word lines and hierarchical IO lines.
As a result of investigations that were carried out subsequent to the completion of the present invention, Unexamined Patent Publication No. Hei 2(1990)-308489 (hereinafter called xe2x80x9cprior art 1xe2x80x9d), Unexamined Patent Publication No. Hei 9(1997)-205182 (corresponding to U.S. Pat. No. 5,793,664 and hereinafter called xe2x80x9cprior art 2xe2x80x9d), and Unexamined Patent Publication No. Hei 10(1998)-178158 (corresponding to U.S. Pat. No. 5,949,697 and hereinafter called xe2x80x9cPrior art 3xe2x80x9d), which are considered to be related to the technical subject matter of the present invention, were discovered. The prior art 1 discloses an arrangement wherein intermediate amplifiers (sub amplifiers) are provided outside each of a plurality of memory cell arrays. The prior art 2 discloses an arrangement wherein N channel type MOSFETs and P channel type MOSFETs of a sense amplifier control circuit are distributively disposed at a cross portion where a sense amplifier row and a sub-word driver column intersect. The prior art 3 discloses an arrangement wherein switch means for connecting GIO (Global Input/Output lines) and LIO (local Input/Output lines) brought into a hierarchical structure are distributively disposed in a conjunction area where a sense amplifier row (sense amplifiers) and a sub-word driver column intersect, and pairs of P channel type driver MOSFETs and N channel type driver MOSFETs of the sense amplifiers are disposed in the same conjunction area. However, none of these publications discloses or gives any consideration to a hierarchical 10 structure according to the present invention, which is to be described later in this application.
The applicant of the present application has developed a dynamic RAM wherein word lines are divided by sub-word driver areas, bit lines are divided by sense amplifier areas, local input/output lines respectively connected to the bit lines are disposed in each of the sense amplifier areas, main input/output lines are disposed in each of the sub-word driver areas, and sub amplifiers for connecting the local input/output lines and main input/output lines and for performing signal amplification are distributively disposed in a cross area where the two intersect. In order to reduce the chip size of such a dynamic RAM (hereinafter called simply a xe2x80x9cDRAMxe2x80x9d), shrinkage in the sub-word driver area and sense amplifier area, which results in an increase in the number of repetitions, is unavoidable. As a result, the size of the cross area is drastically reduced in association with reductions in the sense amplifier width and sub-word driver width. It is therefore difficult to ensure an area for forming the sub amplifiers which perform the selective connections of the local input/output lines and the main input/output lines and the signal amplification.
Signals for selecting column switches for respectively connecting the main input/output lines, that are provided along the sub-word drivers and the bit lines to which each individual selected memory cells are connected, to the local input/output lines, that are provided along each sense amplifier, are set so as to extend in parallel with the main input/output lines. In a burst mode of the DRAM, the signals for selecting the column switches are sequentially switched to perform reading and writing of plural bits. However, since, at this time, the main input/output lines and the column-switch select signals are placed so as to be aligned in the same direction, the column-switch select signal would result in the generation of line-to-line noise in a signal read from or written into the corresponding memory cell connected to each of the bit lines respectively selected by the column-switch select signals, thus causing a problem in that operating margin is reduced.
An object of the present invention is to provide a semiconductor memory device having a hierarchical IO structure, which has achieved high integration and stabilization of its operation.
Another object of the present invention is to provide a semiconductor memory device having a hierarchical 10 structure, which has achieved high integration and increased speed of operation.
The above, other objects and novel features of the present invention will become apparent from the description provided in the present specification and the accompanying drawings.
A summary of typical embodiment of the invention disclosed in the present application will be described in brief as follows. Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines are connected through bit lines, and first selection circuits associated with said sense amplifier areas are provided. Second common input/output lines are connected through the plurality of first common input/output lines, and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended in the second direction to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.
A summary of another typical of the invention disclosed in the present application will be described in brief as follows. Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines are connected through bit lines, and first selection circuits associated with said sense amplifier areas are provided. An amplifier circuit for transferring a signal between each of the plurality of first common input/output lines and at least one second common input/output line, both associated with a plurality of memory arrays disposed along the first direction according to a select signal, is used to configure each of a plurality of second selection circuits. Such an amplifier circuit comprises a sub amplifier for reading, comprising differential type first and second MOSFETs having gates to which the first common input/output lines are connected, and having drains cross-connected to the second common input/output line, third and fourth MOSFETs which are respectively provided at the sources of the first and second MOSFETs and each of which forms an operating current according to a select signal, and a fifth MOSFET which is provided between the sources of the differential MOSFETs and is turned off upon at least a write operation, and a CMOS buffer for writing, comprised of a pair of devices consisting of a P channel type MOSFET and a N channel type MOSFET for driving the first common input/output lines in response to complementary signals from the second common input/output lines.